Future Electronics – Managing Jitter and the Use of the Latest Generation of PLLs

By: Pawel Kaczynski, Central Applications Manager (Advanced Engineering Group), Future Electronics

Today’s consumers are voracious users of network bandwidth. YouTube, streamed TV and movies, online game-playing and other popular applications have led to a huge growth in traffic on the internet, and hence to a requirement for switches, routers and other networking gear that can operate at new high frequencies to support higher data rates.

This phenomenon is not restricted to the telecommunications world; in the computing, industrial, automotive and military/aerospace sectors, the requirement for faster transmission and processing of more data is a common theme.

For system designers working in these sectors, signal integrity is a critically important issue, and this has led to a concentrated focus on the implementation of high speed timing systems. An ineffective timing circuit can often be found, in telecommunications systems for instance, to be the root cause of signal-integrity problems such as excessive bit-error rates.

Jitter – the deviation of a real-world signal’s timing from its ideal state – is one of the most common causes of such problems in timing circuits (see Figure 1). The technical definition made by the US National Institute of Standards and Technology (NIST) is ‘the short term phase variation of the significant instants of a digital signal from their ideal positions in time.’

This can be expressed mathematically as:
Φ = tn-Tn

Where Φ is the jitter, tn is a significant instant of a signal, and Tn is the ideal position in time of this signal.

This article explores the phenomenon of jitter, and describes counter-measures using new components that help to eliminate it or nullify its impact on system performance.

One Disease, Many Symptoms
Jitter might be a familiar term, but in fact it can be used to cover a wide range of different problems to do with timing in electronic circuits. Phenomena described as ‘jitter’ may be measured in either the time domain or the frequency domain; in each case, there are multiple types of timing fault that can be described as jitter.

Figure 1: jitter is a broadly applicable term for inaccuracies or inconsistencies in a signal’s timing or phase

Figure 1: jitter is a broadly applicable term for inaccuracies or inconsistencies in a signal’s timing or phase


A system’s signal integrity will be impaired by jitter to a greater or lesser extent depending on the magnitude of the jitter and the speed of operation of the system. In high data-rate applications, designers are commonly required to attenuate jitter. In order to do so successfully, it is necessary to know how the jitter is generated.

Figure 2: phase noise as a frequency function

Figure 2: phase noise as a frequency function

In fact, there are many potential sources of jitter, so isolating the most important sources is not always straightforward. However, the main sources are likely to be:

  • the power supply – ripple current, parasitic capacitances and magnetic interference caused by switching operations can all disturb timing circuits
  • crystal oscillators – a certain level of jitter will be inherent to the device, and this might be magnified over time or temperature
  • PCB tracks – crosstalk might interfere with timing operations
  • components on the PCB – magnetic devices are particularly prone to generating interference that causes jitter

Fortunately, various methods can help to reduce the magnitude of jitter generated by each of these sources.

The first of these is one that designers should already be implementing anyway: good board layout. It is sensible to start with this, since curing jitter this way entails no additional bill of materials cost. Layout practices that help to reduce jitter include:

  • Managing the routing and termination of long tracks. At high frequencies, a simple PCB track acts like a transmission line in a communications network, and can therefore give rise to crosstalk and signal attenuation. The board designer must therefore take care to match the impedance at each end of each track, and route signal paths properly so as to minimize crosstalk (for instance, by using twisted-pair configurations).
  • Stacking layers appropriately (in a multi-layer PCB). Small signals should be accommodated in the middle layers. The top and bottom layers should contain the power and ground planes.
  • Isolating the power supply (see Figure 3). A voltage regulator’s potential to disrupt a timing circuit can be gauged by studying its Power Supply Rejection Ratio (PSRR) specification. An isolated copper area, known as an ‘isolated power island,’ separates noisy power supplies from the main power plane with capacitors connected in parallel and a ferrite bead in series.
Figure. 3: a power island isolates the rest of the circuit from noise generated by the board’s power planes

Figure. 3: a power island isolates the rest of the circuit from noise generated by the board’s power planes

Nevertheless, there are limits to the effect that layout modifications can have on the disturbance caused by jitter. In particular, mechanical or electronic design requirements prevent the designer from implementing an optimal layout, in terms of interference. For instance, product marketers might place a higher priority on size reduction than on noise reduction; or the I/O configuration to and from the main controller or processor might dictate the routing of critical tracks.

This then entails the adoption of other methods to avoid distortion of high speed timing signals. One is to use a Phase-Locked Loop (PLL) timing device to attenuate jitter. Indeed, discrete PLLs are widely used to provide a clean clock signal in high speed applications. It is important, however, to use the PLL in the right way. In particular, its bandwidth must be optimized.

A PLL’s output jitter depends on two things: imported reference noise, and internal Voltage Controlled Oscillator (VCO) noise. The first is an accumulation of jitter inherent in the reference timing source, plus noise from the PCB and the power supply. The second, VCO noise, consists of noise from the loop filter and VCO amplifiers, as well as noise from the power supply.

If the designer reduces the loop filter’s bandwidth, then more of the jitter generated by the reference clock will be attenuated. This means that if a greater part of the total jitter comes from imported reference noise, then a low PLL bandwidth is recommended.

But this is not a practice that can be applied universally. In general, decreasing the PLL bandwidth tends to increase VCO noise. So in fact the PLL’s bandwidth needs to be balanced in order to minimize the total effect of VCO noise and imported reference noise. The decision about the extent to which PLL bandwidth should be decreased must therefore be made application by application.

This in turn raises the issue of VCO selection; should an external VCO be used? Or a PLL with an internal VCO? The use of an external VCO gives the designer the freedom to choose a device with the best specifications and performance. But such a device will tend to be more sensitive to board-level noise (such as magnetic coupling and power supply noise), and also to noise generated by components in a discrete loop filter.

Equally, a PLL with an integrated VCO but external loop filter components which are sensitive to noise could suffer from timing inaccuracy. Again, the decision must be made on a case by case basis.

Nevertheless, the use of a high quality PLL can achieve a high degree of jitter cleaning in high speed clock signals. For instance, the PureEdge™ Series of PLL-based crystal oscillator modules from ON Semiconductor is intended for use in applications requiring LVPECL/LVDS/CML clock signals, and operating at 2.5V or 3.3V. These modules offer typical RMS phase jitter of just 0.4-0.5ps, making them suitable for most telecoms, networking, computing and storage applications. Indeed, PureEdge devices are widely used in equipment implementing or using technologies such as SONET/SDH, 10Gbits/s Ethernet, LAN, Fiber Channel, PCIe, DIMM, FPGA and SAS/SATA.

It is possible to achieve even lower levels of jitter through the use of cascaded PLL jitter cleaners (attenuators). This technique is effective because it enables the designer to optimize the bandwidth for each of multiple PLLs. It enables designers to realize timing circuits with jitter specified at the level of hundreds of femtoseconds.

Cascaded PLL ICs support a crystal input as well as an external oscillator input. They typically feature up to ten outputs to allow the user to build a full clocking system.

Interesting examples of this type of device are the MAX24605 and MAX24610 from Microsemi Corporation. They include a digital PLL and two independent analog PLLs in a single chip, and feature an output frequency range of up to 750MHz.

In jitter-cleaning applications, they use both digital and analog PLLs in tandem. The advantage of the digital PLL is that its bandwidth is programmable between 4Hz and 400Hz, and a digitally controlled oscillator makes it possible to implement frequency steering in the digital PLL. The provision of two analog PLLs on the same chip enables the generation of two frequency families from the same reference clock, or from two different reference clocks. The MAX24605 and MAX24610 feature a serial peripheral interface, and an on-board EEPROM memory provides for self-configuration after power-up.

The use of a jitter-cleaning device such as these enables the designer to realize a timing circuit with jitter as low as 300fs. As this article shows, the approach to jitter depends on the requirements and limitations of the application. For some, a specific low jitter timing device might not be necessary at all, because good layout practice alone can reduce jitter to an acceptable level.

In applications in which a PLL is required, the designer must take care to specify the bandwidth correctly. In the most extreme cases, ultra low jitter can be achieved through the use of a dedicated jitter cleaning device based on the cascaded PLL topology.

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