Microsemi – SmartFusion2 Evaluation Kit

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Microsemi’s SmartFusion®2 evaluation kit is the lowest cost SoC FPGA platform for developing cost optimized SoC FPGA designs using Microsemi’s SmartFusion2 System-on-Chip (SoC) FPGAs, which integrate inherently reliable flash based FPGA fabric, a 166MHz ARM®Cortex™-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM, and industry required high performance communication interfaces, all on a single chip.

The SmartFusion2 evaluation kit makes it easy to develop transceiver I/O-based FPGA designs to build PCI Express and Gigabit Ethernet-based systems. The board is also small form factor PCIe compliant, which will allow quick prototyping and evaluation using any desktop PC or laptop with a PCIe slot.

The kit enables you to:

  • Develop and test PCI Express Gen2 x1 lane designs
  • Test signal quality of the FPGA transceiver using the full-duplex SERDES SMA pairs
  • Measure the low power consumption of the SmartFusion2 SoC FPGA
  • Quickly create a working PCIe link with the included PCIe control plane demo

The board includes an RJ45 interface to 10/100/1000 Ethernet, 512MB of LPDDR, 64MB SPI Flash, and USB-UART connections, as well as I2C, SPI, and GPIO headers. The kit includes a 12V power supply but can also be powered via the PCIe edge connector. Also included is a free Gold license for the Libero®SoC software toolset to enable FPGA development and to utilize the reference designs made available with the kit. In addition, a FlashPro4 JTAG programmer is included for programming and debugging.

Kit Contents

  • SmartFusion2 SoC FPGA 25K LE M2S025T-1FGG484
  • 12V wall mounted power supply
  • FlashPro4 JTAG programmer for programming
  • USB 2.0A male to mini-B Y-cable for UART/ power interface (up to 1A) to PC
  • Quickstart guide
  • Libero SoC Gold software license
  • PCIe control plane demo design*

Hardware Feature Overview

  • 25K LE SmartFusion2 SoC FPGA in the FGG484 package (M2S025T-1FGG484)
  • 64Mb SPI Flash memory
  • 512MB LPDDR
  • PCI Express Gen2 x1 interface
  • Four SMA connector for testing of full-duplex SERDES channel
  • RJ45 interface for 10/100/1000 Ethernet
  • JTAG/SPI programming interface
  • Headers for I2C, SPI, GPIOs
  • Push-button switches and LEDs for demo purposes
  • Current measurement test points

Demo Design Features

  • DMA data transfers between the Host PC memory and the LSRAM and the DDR memory
  • Throughput for every DMA data transfer
  • Enables continuous DMA transfers for observing throughput variations
  • Displays the PCIe link enable/disable, negotiated link width, and the link speed on the PCIe_Demo application
  • Interrupts the Host PC, when the push-button is pressed; the PCIe_Demo application displays the count value of the number of interrupts sent from the board

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* This demo highlights the high speed data transfer capability of SmartFusion2 and IGLOO2 devices through the PCIe interface. To achieve the high speed data transfers, an advanced extensible interface (AXI) based direct memory access (DMA) controller is implemented in the FPGA fabric. An application, PCIe_Demo that runs in the Host PC is provided for setting up and initiating DMA transactions from the SmartFusion2 or IGLOO2 PCIe endpoint to the Host PC device. Drivers for connecting the Host PC to the SmartFusion2 or IGLOO2 PCIe endpoint are provided as part of the demo deliverables.

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