Micrel – PL902, PL903 and PL904: Straight Talk About Jitter Talk

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Jitter is typically a variation in cycle length or phase of a clock signal. These phase variations are partly random and partly deterministic or periodic.

Jitter and phase noise are essentially the same, wherein one looks at jitter in the time domain and phase noise in the frequency domain. The random variations are mostly caused by thermal noise and the deterministic variations are from cross talk with other signals. With high-end, low noise clocks one sees mostly random noise when a lot of effort was expended to prevent deterministic components in the jitter. Random jitter can be higher in ‘lower-end’ clocks, but usually, when period jitter gets to levels such as 300ps peak-to-peak, it is dominated by deterministic jitter. This is what happens with clocks generated by ICs that process a variety of signals. Take an FPGA for example; there may be many other signals inside the FPGA that can cross talk to the generated clock and period jitter worse than 300ps peak-to-peak can occur. General purpose, multi output, multi PLL clock generators can also generate clocks with rather large period jitter. This is again caused by many different signals sharing the same silicon and power domains and cross talk causing deterministic jitter. This article will discuss the various causes of jitter and how best to manage the condition.

Time synchronizing systems such as IEEE1588 or time reference systems like GPS can generate clocks with a very accurate frequency, adopting the accuracy of the system’s reference clock. These systems ‘assemble’ this clock with time slices to assure an accurate average frequency.

Unfortunately the addition and removal of time slices causes very significant jitter. Period jitter in excess of 20,000ps peak-to-peak has been observed. See Figure 1 below with a waveform of a 10MHz clock from an IEEE1588 system.

Figure 1: The deterministic jitter from adding and removing discrete time slices is clearly visible.

Figure 1: The deterministic jitter from adding and removing discrete time slices is clearly visible.

Jitter attenuating devices have been around for a while and are used to clean up noisy clocks. These devices consist of a synthesizer that recreates the incoming clock but with as little as possible jitter and phase noise in the output clock. The synthesizer locks to the incoming clock with a slow lock (low phase locked loop bandwidth) that avoids passing most of the jitter and phase noise to the output clock. Frequently, a jitter attenuator locks a voltage controlled crystal oscillator to the incoming clock for good phase noise performance. Jitter attenuators require external components such as a crystal and loop filter components. One can also use jitter attenuator modules with the whole jitter attenuating circuit integrated in one unit. However, although this solution does a good job of cleaning jitter, for most applications they are bulky, expensive, and over designed.

To simplify the design process, Micrel has released a series of ”JitterBlocker” ICs that are small, very simple to use, and require the addition of no external components such as crystals or loop filter components. In addition, these devices also offer the multiplication of the incoming signal to up to 850MHz. The designer need only apply power and an input clock to create cleaned up output clocks. JitterBlockers are programmed at the factory for the best possible jitter blocking performance in any specific application. Micrel currently offers three variations.

Micrel’s PL902, for example, focuses on single ended clocks with very large amounts of jitter such as the clock from an IEEE1588 system. In this case, the Micrel solution would reduce the jitter to below 100ps peak-to-peak. Figure 2 shows a 10MHz IEEE1588 clock at the input of the PL902 and the PL902 output clock.

Figure 2: 10MHz IEEE1588 clock from JitterBlocker input to JitterBlocker output.

Figure 2: 10MHz IEEE1588 clock from JitterBlocker input to JitterBlocker output.

The PL902 JitterBlocker is available in a small SOT23 package and does not require any external components. The PL902 is also very suited to clean clocks generated by an FPGA or ASIC. Figure 3 shows a jitter histogram of a clock with 460ps peak-to-peak of period jitter that is reduced to only 75ps peak-to-peak after passing through the PL902.

Figure 3: Deterministic/jitter at JitterBlocker input cleaned up at JitterBlocker output

Figure 3: Deterministic/jitter at JitterBlocker input cleaned up at JitterBlocker output

The PL902 JitterBlocker is factory programmable and can be configured to clean clock frequencies between 1MHz and 200MHz with single ended CMOS logic. Frequency translation is possible so the designer can take a ”dirty” 10MHz clock for example and turn it into a clean 50MHz clock. The PL902 also has fan-out capability with up to three clock outputs.

Micrel’s PL903 and PL904 JitterBlockers focus on phase jitter cleaning with differential or single ended clock outputs. This function is performed by attenuating spurious components in the phase noise and to lower the phase noise floor to achieve enhanced phase jitter. The PL903 and PL904 also do not require any external components to aid the jitter attenuation, so it is easy to insert them into a clock path that requires cleaning. Figure 4 shows an example phase noise plot of a clock with a large spurious signal from cross-talk with other signals.

Figure 4: Spur at JitterBlocker input attenuated and phase noise floor lowered

Figure 4: Spur at JitterBlocker input attenuated and phase noise floor lowered

In this example, the spurious signal dominates the phase jitter with a value of 4.9ps RMS. After passing through the JitterBlocker, the spurious signal is attenuated with more than 20dB and the noise floor at 10MHz from the carrier has also dropped significantly. The result is just 0.46ps RMS of phase jitter in the output clock.

Systems such as Giga-bit Ethernet require differential clocks with very low phase noise at frequencies such as 156.25MHz. Micrel’s PL903 and PL904 are well suited to clean up these clocks in case cross-talk has added spurious signals to the phase noise. Through factory programming, the output logic of the PL903 and PL904 can be set to LVDS, HCSL, LVPECL or LVCMOS. Customization through programming also allows frequency translation. For example, an input clock of 156.25MHz can be cleaned and converted to 625MHz at the same time. The maximum output frequency for the PL903 and PL904 is 850MHz. The PL903 is available in a 4 x 4mm QFN package and the PL904 is available in a 5 x 5mm QFN package.

Summary
With these JitterBlockers, Micrel has simplified jitter attenuation and made it significantly less expensive. This makes jitter cleaning affordable for most systems. Using the example of a clock from the IEEE1588 system, Micrel’s PL902 that fits in a small SOT23 package, can reduce 20,000ps-pp of period jitter to 100ps-pp. The PL903 and PL904 can reduce pico seconds of phase jitter to the femto seconds required for systems such as Giga-bit Ethernet. The JitterBlockers do all this without the need for external components like crystals or loop filters.

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