Renesas – RZ/T1 Real-time Performance for Industrial Drives

Renesas RZ:T1
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Contemporary real-time embedded systems used for servo drives need high-performance architectures to implement field oriented control algorithms that use high carrier frequencies. When this is combined with position loop and is used with trajectory generation, the computational load increases. The processor bandwidth also increases when a second axis of motion is added to the system.

Many current MCU solutions run out of processor bandwidth in this application area, and FPGA plus MCU or an FPGA and a soft-core based solution can be used to mitigate this problem. But, this also leads to higher system cost and complexity. Another potential solution to this is to use an MPU with more processor bandwidth. The issue here is that as the CPU clock rises, the memory system cannot keep up and either wait states are introduced or high-speed cache memory is typically used. Cache 600MHz Cortex R4F CPU plus Tightly Coupled Memory (TCM) Engine Motor Encoder I/F memory is problematic in a hard real-time system because it lacks the determinism needed for a bounded execution time. A typical application will use more program and data that will fit in cache. If there is a cache miss, the code or data must be loaded from slower memory, and this causes execution times to vary. Typical MPU ARM cores also lack a vectored interrupt controller, which causes the software to do more processing to find the interrupt source and dispatch the proper interrupt service routine. The combination of the effects of cache memory and the interrupt controller results in non-deterministic behavior and unbound execution time if multiple interrupts occur.

Today’s High-speed Real-time Solution
The Renesas RZ/T1 was designed to solve this issue by using a Cortex R4F core (see image above). The R4F core features a nested vector interrupt controller as well as tightly coupled memory (TCM). The vectored interrupt controller will dispatch to the proper interrupt handler directly through the vector table via hardware, which minimizes the interrupt latency. The TCM is attached directly to the core at the same memory hierarchy as cache memory. The RZ/T1 is an ideal MPU for demanding hard real-time systems because of its low interrupt latency vectored interrupt controller and low jitter as a result of the use of TCM (see below).

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