The trend in high speed data networks continues to push for higher data rates over longer transmission distances, and under ever-harsher conditions, including electrically noisy environments, large ground potential differences, and high operating temperatures. This article examines signal degradation on the bus and key transceiver requirements for reliable high speed transmission, and then wraps up with design tips for system and bus node designs, along with a set of general high speed design guidelines.
Signal Degradation Through Jitter
High speed RS-485 data links are limited in cable length because of signal degradation in the form of jitter. Both driver and receiver pulse skews and pattern dependent cable skew are what causes signal jitter. Driver and receiver pulse skew are the difference in propagation delays for the rising and falling edges of the driver and receiver. This skew determines the pulse distortion occurring between the single-ended input and the differential output of a driver, and between the differential input and the single-ended output of a receiver. The total pulse distortion is the sum of the skews through the Tx and the Rx in the signal path.
Bit-pattern dependent cable skew is the variation of signal rise and fall times on the bus caused by varying bit sequences of ones and zeros. Patterns with long strings of the same bit charge the cable capacitance to the maximum level and will have a disproportionate fall and subsequent rise time when a bit changes. Patterns like a clock signal have equal charge/discharge times and a more consistent, although smaller, amplitude. Data pulses respond to bit-pattern dependent skew with a loss in amplitude, rounded edges, displacement in time, and a “smearing” of the pulse into adjacent bit intervals.
Measuring the signal transitions over a wide range of pseudo random binary sequence (PRBS) data yields an eye-pattern (see Figure 1), which allows a visual assessment of the quality of a transmission link. The wider the eye opening, the smaller the jitter. Jitter is expressed as a percentage and is defined by the ratio of jitter width (in seconds) to bit width (in seconds):
Jitter(%) = 100 x Jitter width(s)/Bit width(s) EQ.1
In order to reduce jitter, data coding schemes can be applied to remove the large DC content of long bit sequences of 1s and 0s by introducing more transitions into the data stream. The encoded signal charges and discharges the cable capacitance more equally, and generates more consistent signal amplitudes. However, data encoding shortens the charge and discharge time of the cable capacitance, which in turn lowers the bus signal amplitude.
To counteract the aforementioned signal degradation issues, choose high speed transceivers with large differential output voltages (VOD) and small skews. Large driver VOD overcomes the reduction in signal amplitude due to cable attenuation, data encoding and common mode loading (result of ground potential differences), and ensures sufficient noise margin at the remote receiver inputs.
For low-voltage designs, be careful using so-called “Poor Man’s” 3V transceivers (see Figure 2) as these have poorly designed output stages that only provide RS-485 compliant output voltages at supply voltages ≥ 4V. At lower supply rails, the transistor efficiency drastically drops, producing a VOD up to 40% below the 1.5V minimum required by RS-485. Output voltages that low will not yield sufficient noise margin to trigger a remote receiver. Quality devices, like those in Figure 3, meet and exceed RS485 requirements to deliver true 3V RS-485 compliant drive capability even at the highest operating temperatures.
In addition, a small pulse skew minimizes transceiver contribution to the data link’s total jitter budget. Having a small part-to-part skew is also important in synchronous applications, where the clock and data signals come from different transceivers and tight clock-to-data timing must be maintained.
To ease the process of network maintenance or the replacement of defective bus nodes during network operation, use devices that provide hot-plug capability as well as electrostatic discharge (ESD) immunity, conforming to IEC61000-4-2. An IEC-ESD test generator creates transients with much shorter rise times and pulse widths, and significantly higher peak currents than a Human Body Model (HBM) ESD generator, whose application is intended for ESD controlled environments. ESD protection structures designed for IEC61000-4-2 can often tolerate HBM test voltages of up to 2.5 times their IEC test voltage.
System Design Tips
RS-485 recommends the use of unshielded twisted pair (UTP) cable with a characteristic impedance of Z0 = 120Ω nominal. Cables commonly used are either dedicated single-pair RS-485 cables with Z0 = 120Ω or category 5 (CAT-5) cable with four signal pairs and Z0 = 100Ω. When using CAT-5 cable for single pair applications, the three unused signal pairs should be properly terminated to ground with RT = 100Ω at both cable ends. This prevents noise coupling due to self-resonance at all sorts of frequencies from the unused wires into the data pair. When selecting multi-pair cable other than CAT-5, do not use so-called “no-skew cable” as this is not intended for data ransmission but rather for analog signals in high-resolution RGB video systems. Transmitting data signals over this type of cable will result in large crosstalk and data errors.
The RS-485 standard allows for two termination resistors, so high speed data lines should always use termination resistors at both ends of the data link. The value of the termination resistors, RT, should match the characteristic impedance of the cable, Z0, or the characteristic impedance of the controlled-impedance transmission lines on a circuit board: RT = Z0 = 100Ω.
The connection between a transceiver and the main data cable is known as a stub. A stub represents a piece of unterminated transmission line. Stubs must not be terminated in order to avoid excessive bus loading. Instead, their length should be kept short enough to prevent the buildup of signal reflections. A good approximation for calculating the maximum stub length is:
LStub(ft)>tr(s)/10 x v x c EQ.2
where LStub is the stub length (ft), tr is the driver rise time (s), v = signal velocity as a percentage of c, and c = speed of light (9.8 x 10ˆ8 ft/s). The minimum velocities of differential signals are 40% and 60% for FR4 printed circuit board (PCB) material and UTP cable, respectively. To prevent the transmission cable from contributing to stub length, connect the transceivers via daisy chaining to one another (see Figure 4).
Bus Node Design Tips
The pin-out of an RS-485 transceiver is tailored for a straightforward bus node design as the bus terminals are located on one side of the IC, and the single-ended data lines and control lines are on the opposite side. High speed bus nodes require the application of controlled impedance transmission lines to assure low electromagnetic interference (EMI). On the bus side, the differential impedance of the bus traces must match the characteristic impedance of the transmission medium (100Ω or 120Ω). On the control side, the line impedance of the single-ended traces is commonly set to 50Ω.
Controlled impedance lines are accomplished through well-defined trace geometries (length, width, height, and trace spacing) and close electrical coupling with a low-inductance reference plane, either ground or power. For complex designs, use a field solver program to calculate characteristic impedance, signal speed, crosstalk and differential impedance. In addition to first-order terms such as line width, dielectric thickness and dielectric constant, second-order terms such as trace thickness, solder mask and trace etch-back can be considered. A bus node consisting of a transceiver and controller is simple to design. However, the design quickly becomes more complicated when additional components such as surge resistors and transient suppressors for lightning protection are added. If accommodating the additional components results in a change in the impedance of the traces, it constitutes an impedance discontinuity and causes reflections and EMI. Discontinuities might be unavoidable but should be lumped together to keep their area small.
A minimum of four layers are required to accomplish a low EMI PCB design. Layer stacking should be in the following order (top-to-bottom): high speed signal layer traces, ground plane, power plane and control signal layer, low speed traces. Routing the high speed traces on the top layer avoids the use of vias and allows for clean interconnects, while the solid ground plane below it establishes controlled impedances for transmission line interconnects and provides an excellent low-inductance path for the return current flow. Placing the power plane below the ground plane creates additional high-frequency bypass capacitance. Routing the slower speed control (enable) signals on the bottom layer nearly eliminates crosstalk from the high speed data traces.
General High Speed Design Guidelines
1) Use the smallest size possible for signal trace vias and connector pads so they have less impact on the 120Ω differential impedance. Large vias and pads can cause the impedance to drop below Z0.
2) Use solid power and ground planes for impedance control and for minimum noise on the transceiver’s power supply lines.
3) Keep the trace electrical length between the RS-485 connector and the transceiver as short as possible to minimize attenuation and reflection.
4) Place bulk capacitors (e.g., 10μF) close to power sources such as voltage regulators, or place them where the power is supplied to the PCB. Place small 0.1μF and 0.01μF decoupling capacitors at the transceiver VCC pin.
5) If vias are required, use multiple vias when connecting VCC, GND, decoupling caps, and TVS diodes to high speed ICs.
To overcome the signal degradation issues of high speed data networks exposed to harsh environments, designers must pay careful attention to the system design and board layout and use devices that provide exceptionally high output drive capability and highly accurate switching performance, such as the ISL3159E. These devices provide robustness through hot plug capability and 15kV IEC61000-4-2 ESD immunity, and come in a 3 x 3mm DFN package with a wide operating temperature range from -45°C to +125°C.