Future Electronics – kW Fully Digital AC-DC Power Supply with Active Clamping

Mario Di Guardo, Ivan Massimiani

Designers of power-conversion circuits today have to comply with strict energy-efficiency regulations. AC-DC converters for use in telecoms equipment in particular have to meet tough requirements for efficiency from light loads up to full load, and across the universal mains input-voltage range. At the same time, users are calling on OEMs to develop power supplies which are more compact as well as more efficient.

The traditional approach uses a boost PFC stage and a regulation stage, both controlled by analog PWM controllers. More recently, fully digital implementations have been developed which rely on the use of microcontrollers to control both the PFC and the DC-DC conversion stages. This digital approach is increasingly being used for high-density, high-efficiency power electronics systems that will benefit from flexible control and monitoring capabilities.

Digital control offers several advantages to the user of a Switched-Mode Power Supply (SMPS):
• Programming flexibility – it is possible to update and improve the control logic, change the operating point on-the-fly, and tune the control scheme without modifying the hardware design.
• Integration of communication functions and the control algorithm in a single IC. The system can continuously monitor and report on its status using standard protocols such as PMBUS/SMBUS, CAN, PROFIBUS and Ethernet, and provide intelligent fault protection.
• A Graphical User Interface (GUI) may be used to configure and program the system
• Sophisticated functions such as non-linear and multi-variable control techniques, programmable in-rush control, and soft-start may be implemented.

All the advantages of a fully digital AC-DC converter solution may be seen in a reference design developed by STMicroelectronics for a 2kW AC-DC power supply implemented on the STEVAL-ISA172V2 board. Its block diagram is shown in Figure 1. The solution provides a 48V DC output from a universal mains AC input, achieving a high power factor of close to unity.

The system consists of two power stages controlled by two separate STM32F334 MCUs: an interleaved PFC stage, and an output-regulation stage implemented with a phase-shifted full bridge and Synchronous Rectifier (SR).


Figure 1. Block diagram of the 2kW AC-DC power-supply reference design

The PFC circuit is comprised of two boost converters driven by two 180° phase-shifted 60kHz PWM controllers generated by a High-Resolution Timer (HRTIM), a power-conversion peripheral of the STM32F334.

The DC-DC converter stage steps the voltage down from 400V to 48V using a full bridge and a high-frequency transformer with a primary-to-secondary turns ratio chosen to maintain good efficiency and regulation in all conditions. The transformer is supplied with a voltage the average value of which is dependent on the phase shift applied to the 100kHz PWM controllers of the primary-side active switches. On the secondary side, this voltage waveform is rectified and then smoothed by the output filter.

Two elements of the system in particular help this power supply to achieve high efficiency:
• On the primary side, Zero-Voltage Switching (ZVS) keeps switching losses to a minimum.
• On the secondary side, synchronous rectification results in low conduction losses.

Serial communication via optocouplers provides for isolated bi-directional communication between the primary and secondary sides.

Interleaved PFC Circuit
The PFC stage consists of a line bridge rectifier and two boost converters. Control of the circuit is achieved by measuring the current on the two converters via the STM32F334 MCU’s ADC. Another way of achieving the same end is to apply an average control scheme using the signal obtained from a shunt resistor.

The choice of power semiconductors fundamentally affects the efficiency of the entire application. In this reference design, two STW56N60M2-4 N-channel 650V power MOSFETs from STMicroelectronics operate as PFC switches, driven by a PM8834 gate driver. The MOSFETs generate low switching and conduction losses, because of their low maximum on-resistance of 45mΩ at 25°C, and total gate charge of just 91nC at 52A/480V.

In addition, the boost diodes are STPSC1006 Silicon Carbide (SiC) devices, the behavior of which is very close to being ideal: negligible reverse-recovery time, low forward voltage and a high maximum operating temperature of 175°C.

PFC Control Algorithm
The control algorithm of the interleaved PFC stage runs in the STM32F334 MCU. There are two different control loops:
• An outer voltage loop, running at twice the mains frequency – that is, 100Hz or 120Hz – which regulates the bus voltage to the reference value of 400V, thereby setting the correct current reference.
• An inner current loop, operating at up to 60kHz, which minimizes the error between the average inductor current and its sinusoidal reference in phase with the mains voltage.

A phase-locked loop is used to determine the amplitude and phase of the mains voltage; the electrical angle is then used to reconstruct the sinusoidal input-current reference (which is needed to obtain the DC voltage level at the desired value), in phase with the input voltage, thus maximising the power factor regardless of any input-voltage distortions.

This PFC stage works properly not only in continuous-conduction mode but also in the discontinuous-conduction mode, which occurs when supplying light loads or when the mains voltage is near its zero-crossing point. The feed-forward control technique implemented in this reference design achieves a lower value for total harmonic distortion and makes the transient response faster, reducing the output-voltage overshoot caused by input-voltage changes. The control algorithm is also able to shift the current reference in case it is necessary to compensate for sampling delays while maintaining a power factor close to unity (see Figure 2).

Figure 2. The reference design achieves a very high power factor at 120V and 230V across a wide range of load values

Figure 2. The reference design achieves a very high power factor at 120V and 230V across a wide range of load values

ZVS DC-DC Converter
The DC-DC converter stage is a full bridge phase-shifted step-down converter, driven by a phase-shifted modulation scheme with a push-pull output stage.

The purpose of the DC-DC converter stage is to step down the PFC output voltage from 400V to 48V and to provide galvanic insulation with a high-frequency transformer. This modulation scheme was chosen to enable the implementation of ZVS and to minimize turn-on switching losses, making it ideally suited to high-power and high-frequency applications; by contrast, classic PWM modulation produces hard switching and high power losses.

Each leg of the converter is implemented by a STW35N60DM2 600V power MOSFET from ST’s MDmeshTM DM2 series. It combines a very low reverse-recovery charge and reverse-recovery time with low on-resistance and capacitance, making it ideal for bridge topologies and ZVS phase-shift converters.

Each leg of the full bridge is driven by two complementary 100kHz PWM signals from the HRTIM with a fixed 50% duty cycle, using a PM8834 gate driver in combination with two pulse transformers. The secondary-side STM32F334 MCU implements the modulation scheme by delaying in phase the two square waves of the lagging leg with respect to the leading leg. The HRTIM’s 217ps resolution results in very precise output-voltage regulation.

Synchronous Rectification Increases Efficiency
The SR circuit is used to improve the efficiency of the DC-DC converter. Instead of the conventional output diodes, the SR circuit uses 200V STW75NF20 MOSFETs controlled by the secondary-side STM32F334 MCU and driven by another PM8834 gate driver. To avoid cross-conduction in the SR MOSFETs, a delay time has to be introduced between the beginning of diode conduction and the command sent to the MOSFET gate. It is important to optimize the delay time of the MOSFET, which can be different for the rising and falling edges of the two switches, in order to minimize the duration of diode conduction and to improve efficiency.

Active-Clamp Circuit Protects the Power Supply
The converter circuit described here stores unwanted energy in the transformer – the result of leakage inductance – and the diode, in the form of reverse-recovery charge. This energy could be released as high-voltage spikes on the SR MOSFETs, so some form of protection is required.

An RCD snubber circuit on this type of converter might provide insufficient protection to properly clamp the over-voltage. Furthermore, an RCD circuit introduces additional thermal dissipation and impairs the system’s efficiency. For this reason the STEVAL-ISA172V2 evaluation board includes two active-clamp circuits, driven by the secondary-side MCU, which reverse the stored energy directly to the output. This eliminates dissipative losses and results in better efficiency.

As the MOSFET turns off, the over-voltage is clamped by the charge in the clamp capacitor; this capacitor is then discharged by an active resonant circuit which operates as a buck converter using two 600V STP24N60DM2 MOSFETs driven by a PM8834 dual low-side MOSFET driver.

Figure 3. Currents and voltages through the active-clamp circuit

Figure 3. Currents and voltages through the active-clamp circuit

Figure 3 shows the SR MOSFET voltage (yellow trace), the clamp capacitor voltage as the spikes are absorbed (red trace), and the voltage and current at the buck inductor (blue and green traces).

High System Efficiency
The overall efficiency of the reference design implemented on the STEVAL-ISA172V2 board has been measured at different loads. The input and output voltage and current were measured directly at the board’s connectors. Efficiency peaks at near 92% at around 1kW of output power from a 230V AC input (see Figure 4).

Figure 4. Total efficiency of 2kW power supply reference design at various loads

Figure 4. Total efficiency of 2kW power supply reference design at various loads

This reference design shows how digital control, implemented with 32-bit MCUs from the STM32F family, offers a flexible control strategy, allowing the use of advanced control techniques such as the feed-forward algorithm, while allowing for additional improvements to the control logic as well as easier tuning of the control system without modifying the hardware.

Measurements of the operation of the reference design on the ST evaluation board show that it offers:
• High efficiency
• Power factor near unity
• Low total harmonic distortion over a wide range of input voltages and loads

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