Lattice Semiconductor – Comparing Circuit Board Power Management Architectures

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Power management architectures used in circuit boards can be broadly classified into 5 types (Figure 1 through Figure 5). Some designs combine one or more architectures to overcome the individual limitations of each architecture. Typically, circuit board payload components (ASIC/SOC/CPU) and the input power supplies determine both the power network as well as the management of DC-DC converters used in that power network.

The term Power Management in this context refers to:
1. Rail voltage fault monitoring, measurement, and sequence control of DC-DC controllers used in the power network
2. Generation of digital control signals such as reset and power OK signals for the payload devices

In addition, most circuit boards use a Control PLD (C-PLD) to integrate other housekeeping functions such as JTAG, I2C, legacy logic, level translation bridging and other board control functions. This control PLD may be a macrocell based PLD or a C-PLD or a small FPGA.

This article uses a typical hierarchical power network to compare different power management architectures. In this power network three classes of DC-DC converters are used:
1. Device Supplies – Used exclusively to power the Payload devices
2. Board Common Supplies – Generate voltages shared between multiple payload devices
3. Input Supplies – Convert board input supply voltage to main board rail used by all DC-DC converters

The following section examines 5 basic power management architectures. The table at the end of this article maps major power management design considerations vs architectural benefits.

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Figure 1: Power architecture #1 – power management and housekeeping by C-PLD

Figure 1: Power architecture #1 – power management and housekeeping by C-PLD

Control PLD monitors the supply status using Power-good signals for control signal generation. The sequencing algorithm implemented in C-PLD controls the DC-DC converters through their enable signals. C-PLD designs are implemented in VHDL or Verilog.

PROS

  • Low cost
  • Scalable sequencing
  • Single design environment
  • Event-based architecture

CONS

  • High C-PLD I/O count and board congestion
  • Increased cost for Telemetry support
  • Reduced reliability due to unreliable power good fault detection
  • Requires digital design

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Figure 2: Power architecture #2 – hardware management system implemented using C-PLD and power manager ICs

Figure 2: Power architecture #2 – hardware management system implemented using C-PLD and power manager ICs

Power manager ICs monitor the voltage and control sequencing. C-PLD monitors the supply status using power good signals for control signal generation. Power manager designs are implemented using GUI and C-PLD designs with VHDL or Verilog.

PROS

  • Low C-PLD I/O count
  • Low board congestion
  • High power management reliability

CONS

  • Expensive solution
  • Difficult to scale sequencing/partition across power managers
  • Design spread across multiple tools (GUI + VHDL/Verilog)

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Figure 3: Hardware management system implemented using C-PLD and MCU

Figure 3: Hardware management system implemented using C-PLD and MCU

A microcontroller uses PMBus to perform time based sequencing of digital DC-DC converters (DPOLs). Housekeeping functions, controlling of DC-DC converters without PMBus interface (APOLs) and event based sequencing of DPOLs are handled by the C-PLD. Power management designs are implemented using microcontroller software and the C-PLD design with VHDL or Verilog.

PROS

  • Scalable (for time based sequencing only)
  • Reduced debug time due to debug utilities
  • Routing congestion reduced around DPOLs
  • Modified with firmware updates

CONS

  • More expensive
  • Difficult to scale for event based sequencing
  • Multiple design tools – Verilog/VHDL, software
  • Mix of APOL and DPOL requires hybrid control solution

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Figure 4: Power management and housekeeping by C-PLD with on-chip ADC

Figure 4: Power management and housekeeping by C-PLD with on-chip ADC

C-PLD with an ADC is used to sample all voltages to overcome issues with inaccurate Power-good signal. The C-PLD implements power management using on-chip soft/hard processor core and housekeeping functions using logic. Power Management implemented using software and other housekeeping functions are implemented using VHDL/Verilog.

PROS

  • Scalable solution
  • Reduced design time as power management and housekeeping functions are together
  • Telemetry support

CONS

  • Needs C-PLD with higher density and higher I/O count
  • Increases circuit board congestion
  • More expensive
  • Requires digital engineer to design power

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Figure 5: The L-ASC10 (ASC) remote sensing and controlling element

Figure 5: The L-ASC10 (ASC) remote sensing and controlling element

C-PLD uses an external ASC device to sample all voltages through the serial bus. C-PLD also controls DC-DC enable signals via the ASC through the serial bus. The C-PLD also implements both power management and housekeeping functions. Power Management & housekeeping functions can be implemented using GUI or VHDL/Verilog or both.

PROS

  • Lowest C-PLD I/O count
  • Least board congestion
  • Single design environment
  • Scalable solution
  • Reduced overall cost because ASC integrates voltage, current and temperature monitoring function
  • Reduced design time as power Management and housekeeping functions are together
  • Reduced debug time due to debug utilities
Design ConsiderationsC-PLDC-PLD+Power ManagerC-PLD with On-Chip ADCC-PLD + MCU+PMBusC-PLD + ASC
C-PLD IO Utilization for Power ManagementHighMediumHighLowLow
PCB Routing CongestionHighMediumHighLowLow
Need to route low voltage analog signals to a central location on a PCBNoNoYesNoNo
Ease of use of the architecture from simple to complex boardsEasyDifficultMediumDifficultEasy
C-PLD logic overhead due to power managementMediumNoneVery HighLowMedium
Voltage MeasurementNoYesYesYesYes
Ability to prevent on-board payload device operation under faulty power supply conditionsPoorBetterBestPoorBest
Power management design methodologyVerilog/VHDLAnalog GUIVerilog/VHDLC++ or Verilog/VHDLAnalog GUI or Verilog/VHDL or Both
Design tools - power engineer friendly?NoYesNoNoYes
Availability of board power management section debug toolsNoLimitedNoLimitedYes
Time required for debugging board power management sectionHighMediumHighMediumLow
Overall cost of implementationLowHighHighHighLow

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