IDT offers a comprehensive portfolio of PCI Express® (PCIe) clock generators that provide two, four, six or eight outputs. The 9FG timing family targets power- and space-constrained designs in both consumer and high performance applications, providing enterprise level performance while lowering the total cost of ownership.
IDT offers the high-performance 9FG devices in three series: the 9FGU series at 1.5V, 9FGV at 1.8V and the 9FGL at 3.3V. This allows the designer to power their PCIe clock generators from the same power supply as their FPGA or System-on-Chip (SoC).
Clock generators are the gating factor limiting performance and reliability in PCIe-based systems. PCIe is a high speed serial communication interface with data rates up to 8Gbits/s. This will increase to 16Gbits/s when PCIe Gen4 devices become available. As with any serial communication interface, the most critical clock parameter is phase jitter. A PCIe-based system with a lower performance clock may completely fail to train.
More insidiously, the link may train to less than the advertised through- put, or will experience many link errors that require data to be re-sent. In this case, while the system will function, the reduced link bandwidth will degrade performance.
System performance degradation is enhanced by use of the 9FG family clock generators. Every device in the family far exceeds the published PCIe specifications at each performance node – PCIe Gen1, Gen2 and Gen3 – and the 9FGL devices conform to the forthcoming PCIe Gen4 specification. The 9FGL clock generators are also suitable for Gigabit Ethernet and similar applications needing phase jitter of less than 3psrms over a frequency span between 12kHz and 20MHz.
IDT offers the PCIe clock generators with integrated terminations to allow direct connection of the outputs to the transmission line, thus saving a valuable amount of board space. The devices also provide a copy of the reference clock, saving a crystal in the design.
All IDT’s PCIe clock generators support the PCIe Common Clock architec- ture with or without spread spectrum. In addition, the 3.3V 9FGL parts support the Separate Reference no Spread (SRnS) and Separate Reference Independent Spread (SRIS) clock architectures.
- Standard configurations cover the majority of application requirements
- Factory-programmable versions of the 9FGL enable rapid device optimizations for specific applications
- Output-by-output configuration of 9FGL output impedances allow use in mixed environments
- Family supports both 100Ω and 85Ω environments
- Three build in spread spectrum levels: Off, -0.25%, -0.5%
- Multi-function printers
- Set-top boxes
- Solid-state drives
- PCIe add-in cards